Testing is critical to ensuring that manufactured integrated circuits meet certain quality levels. Due to the inherent complexity of modern integrated circuitry, it had become increasingly difficult to test every conceivable combination of circuit states due to the length of time it takes to scan data serially in and out of registers within the circuitry. Testers have endeavoured to reduce these times whilst still providing good coverage by generating libraries of tests for particular circuits that provide acceptable fault coverage in the minimum time. It has been found that tests generated to provide good “stuck-at” fault (in which a circuit point is incorrectly bridged to ground or the power supply) coverage have the corollary of tending to provide good testing of the circuits overall.
Tristate devices are well known in the electronics and computing fields, enabling data to be selectively placed onto a bus when in a first mode, whilst offering a high impedance load to the bus when in a second mode.
An exemplary tristate bus 1 is shown in FIG. 1. Each cell 10 is connected to a bus 11, and includes a data input Dx and an enable input ENx. When the enable input is high, the value of the data input Dx is put onto the bus 11 via an output buffer 12. It will be understood that, in operation, it is important that only a single cell 10 be enabled at any one time, to ensure that there is no conflict on the bus. When the enable input is low, the output of the tristate cell presents a high impedance load to the bus.
The nature of tristate circuitry means that with certain designs, post-manufacture testing can be difficult, especially for stuck-at faults within enable circuitry. For example, in FIG. 3, there is shown a situation in which enable input 30 is stuck-at-0, even though it is being driven by a logical 1. The result of this is that the bus is floating, meaning there is a 50% chance that the fault will not be detected at the output buffer.
Similarly, in FIG. 4 there is shown a situation in which enable input 40 is stuck-at-1. In the event that different data values are output by the cell 41 actually being tested and the cell 42 with the enable input stuck-at-1, the bus is again in an undetermined state. Where the data values on the faulty driver and the enabled drivers are the same (as shown in FIG. 5), the output is as expected, even though the circuit is faulty. A stuck-at-1 fault on an enable line therefore also produces the possibility that the fault will not be detected. Similar problems occur if faults occur anywhere along the lines that supply enable signals to the tristate cells.
Also of concern is bus contention, which arises when two or more enable inputs are enabled and the data they are attempting to put onto the bus are different. This can happen as shown in FIG. 2, where each enable is controlled by a scan chain of flip-flops 20. In use, the state machine of which the flip-flops form part is designed to ensure that only one of the flip-flops is set to a logical 1 in any cycle, ensuring that contention cannot take place. However, during scan chain loading when testing, it is likely that several of the flip-flops in any shift cycle will have a logical 1 value, which can generate contention on the bus.
Also of concern to chip designers is the increasing number of components and blocks that are squeezed onto chips. One problem with this is that during testing, certain states can arise in which the chip draws more current than it is designed to tolerate. This can lead to component failure, or at least overheating. It is therefore desirable to allow testing of blocks within a circuit by disabling one or more other blocks. However, this can provide difficulties when blocks that a tester would prefer to disable must be enable to allow data to pass through them.